Recently, there is an increasing demand for liquid crystal display devices as large screen liquid crystal TVs, in addition to portable telephone terminals (mobile phone, cell phone), notebook PCs, and monitors. In these liquid crystal display devices, a liquid crystal display device of an active matrix drive system that enables a high-definition display is used. First, referring to FIG. 12, an outline is given concerning a typical configuration of a liquid crystal display device that uses the active matrix drive system. It is to be noted that in FIG. 12, a main configuration connected to one pixel of a liquid crystal unit is schematically shown by an equivalent circuit.
In general, a display panel 960 of the liquid crystal display device of the active matrix drive system includes a semiconductor substrate on which transparent pixel electrodes 964 and thin film transistors (TFTs) 963 are arranged in a matrix (for example, in a case of a color SXGA panel, 1280×3 pixel columns×1024 pixel rows), and an opposing substrate that has a transparent electrode 967 formed on an entire surface, and a liquid crystal sealed between with these two substrates which face to each other. It is to be noted that a display element 969 corresponding to one pixel is provided with a pixel electrode 964, an opposing substrate electrode 967, a liquid crystal capacitor 965, and auxiliary capacitor 966.
The TFT 963 which has a switching function, is controlled to be ON/OFF (conductive/non-conductive) by a scan signal. When the TFT 963 is ON (conductive), a gray scale signal voltage corresponding to a video data signal is applied to the pixel electrode 964 of the display element 969, and liquid crystal transmittance changes according to potential difference between each pixel electrode 964 and the opposing substrate electrode 967. After the TFT 963 is turned OFF (non-conductive), an image is displayed by holding the potential difference for a fixed time period by the liquid crystal capacitor 965, and the auxiliary capacitor 966.
On a semiconductor substrate, a data line 962 that transmits plural level voltages (gray scale signal voltages) applied to each pixel electrode 964, and a scan line 961 that transmits a scan signal are laid out in a grid form (in a case of the abovementioned color SXGA panel, there are 280×3 data lines and 1024 scan lines). The scan line 961 and the data line 962 form large capacitive loads, due to capacitance at an intersection thereof and capacitance of the liquid crystal sandwiched between the opposing substrate electrodes.
It is to be noted that the scan signal is supplied to the scan line 961 from a gate driver 970, and that the supply of gray-scale signal voltage to each pixel electrode 964 is performed by a data driver 980 via the data line 962. The gate driver 970 and the data driver 980 are controlled by a display controller 950, and supplied with respectively required clocks CLK and control signals by the display controller 950. Video data is supplied to the data driver 980. At present, digital data is used as video data. A power supply circuit 940 supplies a required power supply voltage respective drivers.
Rewriting of one screen of data is carried out over one frame time period (normally about 0.017 seconds when driving at 60 Hz), a selection is successively made every pixel row (every line) by each scan line, and a gray-scale signal voltage is supplied by each data line within a selection time period. It is to be noted that a plurality of pixel rows may be selected by a scan line at the same time, and driving may be performed with a frame frequency of 60 Hz or more.
Although the gate driver 970 only needs to be supplied with at least a binary scan signal, the data driver 980 is required to drive the data line by gray scale signal voltage of multi-value levels in accordance with the number of gray scale levels. As a result, the data driver 980 is provided with a digital-to-analog converter circuit (DAC) including a decoder that converts video data to analog voltage, and an output amplifier that amplifies and outputs the analog voltage to the data line 962.
For a drive method of driving a large screen display device such as a monitor, liquid crystal TV and so forth, a dot inversion driving system that enables high image quality is employed. The dot inversion driving system, in the display panel 960 of FIG. 12, is a drive system in which the opposing substrate electrode voltage VCOM is a constant voltage, and voltage polarities held in neighboring pixels have mutually opposite polarity. As a result, the voltage polarity outputted to neighboring data lines (962) forms a positive polarity and a negative polarity with respect to the opposing substrate electrode voltage VCOM. It is to be noted that in the dot inversion driving, normally, polarity inversion of data lines is carried out for each one horizontal time period, but in a case of an increase in data line load capacitance or when frame frequency becomes high, a dot driving method in which polarity inversion is performed for each two horizontal time periods is also used.
FIG. 13A is a diagram showing a configuration of an output amplifier circuit (output circuit) for a data driver that drives a data line (refer to Patent Document 1 and the like). FIG. 13B is a timing diagram for describing operation of FIG. 13A.
The output amplifier circuit includes a differential stage 900 having a non-inverting input terminal connected to an input terminal N1; a pMOS transistor M93 having a source connected to a first power supply terminal (VDD), a gate connected to first output of the differential stage 900, and a drain connected to an output terminal N3; and a nMOS transistor M94 having a source connected to a second power supply terminal (VSS), a gate connected to second output (a common phase signal with respect to the first output is outputted) of the differential stage 900, and a drain connected to the output terminal N3; and the output terminal N3 is connected to an inverting input terminal of the differential stage 900. An output switch SW90 (transfer gate) is provided between the output terminal N3 of the output amplifier circuit and a load (data line) 90.
With regard to the output switch SW90, transition noise at a point in time of change of an input signal (analog data) applied to the input terminal N1 is amplified by the output amplifier circuit to be transmitted to the load (data line) 90, and in order to prevent display deterioration, for a prescribed time period (T11) from the start of one data time period, control is usually performed so that the output switch SW90 is turned OFF. In the prescribed time period (T11) in FIG. 13B, the analog data signal finishes a transitioning, in an output time period (T12), the output switch SW90 is ON, and the load (data line) 90 is driven by a gray scale signal voltage outputted from the output amplifier circuit, in response to an input signal Vin.
FIG. 14 is a diagram showing a configuration example of the differential stage 900 of FIG. 13A at a transistor level, which has a folded cascode Rail-to-Rail amplifier configuration, provided with both an nMOS differential pair and a pMOS differential pair. The differential stage 900 is provided with a nMOS differential pair (M11 and M12) and a pMOS differential pair (M21 and M23), driven by first and second current sources (M13 and M23), respectively and a first cascoded current mirror circuit (M14 to M17). The nMOS and pMOS differential pairs have first inputs connected to an input terminal (1), and second inputs connected to an output terminal (2). An output pair of the nMOS differential pair is connected to the first cascoded current mirror circuit (M14 to M17). The differential stage 900 is also provided with a first floating current source (M31 and M32) and a second floating current source (M32 and M34) connected to first and second terminals of the first cascoded current mirror circuit and a second cascoded current mirror circuit (M24 to M37) having first and second terminals respectively connected to a second end of the first and second floating current sources and connected to an output pair of the pMOS differential pair. The second terminals of the first and second cascoded current mirror circuits form first and second outputs of the differential stage 900.
In more detail, referring to FIG. 14, the differential stage 900 includes:
an nMOS transistor M13 (constant current source) having a source connected to a power supply VSS, and a gate connected to a bias terminal BN1;
nMOS transistors M11 and M12 (nMOS differential pair) having coupled sources connected to a drain of the nMOS transistor M13, and gates connected to an input terminal 1 and an output terminal 2, respectively;
a pMOS transistor M23 (constant current source) having a source connected to a power supply VDD and a gate connected to a bias terminal BP1;
pMOS transistors M21 and M22 (pMOS differential pair) having coupled sources connected to a drain of the pMOS transistor M23, and gates connected to an input terminal 1 and an output terminal 2, respectively;
pMOS transistors M14 and M15 having sources connected to the power supply VDD, and gates coupled together;
pMOS transistors M16 and M17 having sources connected to drains of the pMOS transistors M14 and M15, respectively, and gates coupled together to a bias terminal BP2;
nMOS transistors M24 and M25 having sources connected to the power supply VSS, and gates coupled together; and
nMOS transistors M26 and M27 having sources connected to drains of the nMOS transistors M24 and M25, respectively, and gates coupled together to the bias terminal BN2.
The drains (output of the nMOS differential pair) of the nMOS transistors M11 and M12 are connected to drains of the pMOS transistors M14 and M15 (load circuit of the nMOS differential pair), respectively. The drains (output of the pMOS differential pair) of the pMOS transistors M21 and M22 are connected to drains of the nMOS transistors M24 and M25 (load circuit of the pMOS differential pair), respectively. The drain of the pMOS transistor M17 is connected to common gates of the pMOS transistors M14 and M15. The pMOS transistors M14 to M17 form the first cascoded current mirror. The drain of the nMOS transistor M27 is connected to coupled gates of the nMOS transistors M24 and M25. The transistors M24 to M27 form the second cascoded current mirror.
The differential stage 900 includes:
an nMOS transistor M32 and a pMOS transistor M31 connected in parallel between the drain of the pMOS transistor M17 and the drain of the nMOS transistor M27, and an nMOS transistor M34 and a pMOS transistor M33 connected in parallel between the drain of the pMOS transistor M16 and the drain of the nMOS transistor M26. The gate of the pMOS transistor M31 is connected to a bias terminal BP3, the gate of the nMOS transistor M32 is connected to the bias terminal BN3, the gate of the pMOS transistor M33 is connected to a bias terminal BP4, and the gate of the nMOS transistor M34 is connected to the bias terminal BN4. The pMOS transistor M31, the nMOS transistor M32, the pMOS transistor M33, and the nMOS transistor M34 respectively form floating current sources.
A capacitor C3 (phase compensation capacitor) is inserted between the output terminal 2 and a connection node of the pMOS transistor M14 and M16, that is, an output of the nMOS differential pair), and a capacitor C4 is connected between the output terminal 2 and a connection node of the nMOS transistors M24 and M26, that is an output of the pMOS differential pair.
An output stage 110 includes:
a pMOS transistor M93 having a source connected to the power supply VDD and a gate connected to a drain of the pMOS transistor M16 (the second terminal of the first cascoded current mirror circuit), and
an nMOS transistor M94 having a source connected to the power supply VSS and a gate connected to a drain of the nMOS transistor M26 (the second terminal of the second cascoded current mirror circuit). A connection node of drains of the pMOS transistor M93 and the nMOS transistor M94 forms an output node 2 which is connected to a gate of the nMOS transistor M12 of the nMOS differential pair and a gate of the pMOS transistor M22 of the pMOS differential pair. The differential stage 900 and an output stage 100 in FIG. 14 form a voltage follower.
Patent Document 2 discloses a configuration of an offset cancelling amplifier as shown in FIG. 15. Referring to FIG. 15, a differential circuit 10 includes
nMOS transistors M3 and M4 forming a differential pair with sources being commonly connected,
an nMOS transistor M9 (current source) connected to the coupled sources of the nMOS transistors M3 and M4, and
pMOS transistors M1 and M2 having drains connected to drains of the nMOS transistors M3 and M4, respectively and forming a current mirror circuit. There is provided
a pMOS transistor M7 having a source connected to a power supply terminal VDD and a gate connected to the drain of the nMOS transistor M4, and a drain N1 fed back to a gate of the transistor M3 via a switch SW2;
an nMOS transistor M10 (a pull-down current source transistor) having a source connected to a power supply terminal GND, and a drain connected to the drain N1 of the pMOS transistor M7, and a gate supplied with a bias voltage VBB;
a pMOS transistor M11 having a source connected to the power supply terminal VDD and a drain connected to an output terminal OUT;
an nMOS transistor M12 having a source connected to a power supply terminal VSS and a drain connected to the output terminal OUT;
a pMOS transistor M13 connected between a gate of the transistor M7 and a gate of the transistor M11, and having a gate connected to a control signal CON;
a nMOS transistor M15 connected between a gate of the transistor M12 and a gate of the transistor M10, and having a gate connected to an inverted signal (output of an inverter INV2) of the control signal CON;
a pMOS transistor M14 having a source connected to a power supply terminal VDD, a drain connected to a gate of the transistor M11, and a gate supplied with a signal obtained by inverting the control signal CON by an inverter INV1; and
an nMOS transistor M16 having a source connected to a power supply terminal GND, a drain connected to a gate of the transistor M12, and a gate supplied with a signal obtained by inverting the control signal CON by the inverter INV2 and further inverted by an inverter INV3.
An offset cancel circuit 11 that stores an offset state is connected to the transistors M3 and M4 composing an input stage differential pair. The offset cancel circuit 11 stores a voltage (IN+ΔV) obtained by an offset voltage ΔV being added to an input voltage IN.
The offset cancel circuit 11 includes
transistors M5 and M6 (nMOS) for offset cancellation in parallel to the differential pair transistors M3 and M4,
a current source transistor M8 (nMOS) connected to the coupled sources of the transistors M5 and M6; and
a capacitor C1 for offset cancellation connected to a gate of the transistor M5. A prescribed bias voltage VBB is applied to gates of the three current source transistors M8, M9, and M10.
In an offset cancel time period, the switch SW2 is turned OFF (non-conductive), switches SW1 and SW3 are turned ON (conductive), and the input voltage IN is applied to gates of the transistors M3, M4, and M6. At this time, a gate N2 of the transistor M5 in the offset cancel circuit 11, with a drain N1 of the transistor M7 being fed back via the switch SW3, has a voltage follower configuration with respect to the input voltage IN. As a result, a voltage (IN+ΔV) obtained by the offset voltage ΔV being added to the input voltage IN is stored in the capacitor C1.
Thereafter in an operational amplifier operation time period, the switch SW2 is turned ON, the switches SW1 and SW3 are turned OFF, and the drain N1 of the output transistor M7 is fed back to a gate of the transistor M3. In the offset cancel circuit 11, voltages of the gates of the transistors M5 and M6 are maintained. As a result, the gate of the transistor M3 is stable in a state having the input voltage IN and at the drain N1 of the transistor M7, the input voltage IN is generated.
In addition, the transistor M11 (pMOS) and the transistor M12 (pMOS) (second output stage) are connected in parallel with the transistor M7 and the transistor M10 (first output stage), the switch transistors M13 and M14 (both pMOS) are connected to a gate of the transistor M11, and the switch transistors M15 and M16 (both nMOS) are connected to a gate of the second output current source transistor M12. These switch transistors M12, M14, M15, and M16 are controlled to be turned ON and OFF by the control signal CON and its inverted controls by the inverters INV1, 2, and 3.
In this operational amplifier circuit, when an offset cancel time period is finished, the transistor M11 and the transistor M12 are cut off from the transistor M7 and the transistor M10, and the gates if the transistor M11 and the transistor M12 are connected to the power supply VDD and ground GND, respectively to be set in a non-operation state. That is, by switching the control signal CON from a Low level to a High level, both of the transistors M13 and M15 are turned OFF, and both of the transistors M14 and M16 are turned ON. Then after, a switch SW4 is turned ON to enter an operational amplifier operation time period. As a result, in the operational amplifier operation time period thereafter, a control operation according to an output of the differential circuit 10 with regard to the transistor M11 is stopped, and the transistor M11 is in a non-active state. The output current source transistor M12 similarly is in a non-active state.
FIG. 16 is a diagram showing operation of an output unit of a circuit in FIG. 15. In the offset cancel time period, the switches SW2 and SW4 are OFF, the switches SW1 and SW3 are ON, the transistors M13 and M15 are ON, the transistors M14 and M16 are OFF, and the second output stage (M11 and M12) is activated. The drain node N1 of the output transistor M7 is driven by a voltage that is offset by an offset voltage ΔV from the input voltage IN, and the capacitor C1 is charged by an input voltage of IN+ΔV. In the operational amplifier operation time period, the switches SW2 and SW4 are ON, the switches SW1 and SW3 are OFF, and the second output stage (M11 and M12) is in a non-activated state. The second output stage (M11 and M12) is activated in the offset cancel time period, and signals that are the same as those supplied to respective gates of the first output stage (M7 and M10) are supplied to respective gates of the second output stage (M11 and M12). In this way, by a load capacitor (not shown in the drawing) that is connected to the output terminal OUT being driven as far as approximately the input voltage IN by the second output stage (M11 and M12) in the offset cancel time period, it is possible to speed up the drive speed of the load capacitor (improve the response characteristic of the output voltage). With regard to the final load capacitor drive voltage (output voltage), the voltage (IN), in which the offset voltage ΔV is cancelled is outputted from the first output stage (M7 and M10) in the operating amplifier operation time period.    [Patent Document 1]    JP Patent Kokai Publication No. JP-P2007-47342A    [Patent Document 2]    JP Patent Kokai Publication No. JP-P2003-60453A